The present invention relates to an active clamp circuit used to assist in maintaining proper operation of a current transformer, and more particularly to circuitry to maintain proper current transformer operation in a resonant transition converter circuit or any other circuit having a wide range of reverse current present in a current transformer primary at the beginning of a power pulse.
FIG. 1 illustrates a phase shifted full-bridge converter with FET transistor switches Q1, Q2, Q3 and Q4 operating at a fixed frequency. In order to lower the power dissipation in this circuit zero-voltage switching techniques are implemented where a switch begins conduction with a near zero-voltage existing across the switch.
The "on" time of the diagonally conducting switches (i.e. Q1 and Q4 or Q2 and Q3) is not varied as in a PWM bridge type circuit, rather the switches in a first leg (Q1 and Q2) and a second leg (Q3 and Q4) are made to conduct at a duty cycle approaching 50%. The waveforms for such switching are shown in FIG. 2. The phase shift between the operation of the devices of each of the legs determines when diagonal switches are conducting at the same time and, therefore, supplying power to a load. By varying the phase shift, the resulting output voltage can be pulse width modulated. In the converter, transformer primary current flowing at turn-off of one transistor charges the parasitic capacitance of that transistor while reducing the charge on the parasitic capacitances of the other transistor in the same leg, thereby reducing the voltage across the transistor, which is also the next transistor to be turned on. Obtaining zero-voltage switching requires that the turn-on of the transistor in the same leg with a transistor that was just turned off must be delayed until the voltage across the transistor has been reduced to near zero.
At the moment of turn-off of each transistor switch Q1-Q4, there needs to be present in that switch a lagging current of sufficient amplitude and duration to cause the voltage on that switch to rise to the amplitude of the supply in a totally passive fashion. At heavier loads, this current will be present in the series inductance of the power transformer. At lighter loads, the current may be obtained from energy stored in the shunt inductance of the power transformer.
However, as the load approaches no-load and the phase angle approaches 0.degree., the volt-seconds applied to the power transformer primary approaches zero, and the energy stored in the power transformer primary which is available as a lagging current for resonant transition also approaches zero. In such a situation resonant transition can fail. As the load approaches a no-load situation the currents are basically comprised of inductive currents. Since the current in the power transformer is inductive, the current will ramp up, level off and then it will ramp down in the other direction and then again level off.
It is known that, especially at lighter loads, the currents in the FET switches will have both forward (positive) current and reverse (negative) current. In most circuits current flows only in one direction, for example into the drain of a transistor. In this circuit when the switches are activated by a power pulse reverse current will flow and this reverse current may last as long as half of the power pulse.
It is also known that converters, supplies and many other devices employ current transformers to assist in control operations. Among other applications current transformers are used to indicate transitions or changes, and to measure values including peak values, within a circuit. Benefits of using current transformers for control and limiting applications include their ability to provide good signal-to-noise ratio, isolation between the control circuit and the line being monitored, good common-mode rejection, and that they do not introduce excessive power loss in high-current applications.
In general, for current transformers, the larger the inductance, the smaller the magnetizing current and the more accurate the measurement. The magnetizing current component increases during the pulse duration and will be subtracted from the quantity to be measured. Consequently, at the end of a conduction pulse, the magnetizing current should be small compared with the measured quantity. For current limiting applications, a magnetizing current of 10% is a typical design limit. This magnetization effect is most easily shown in a uni-directional current transformer.
FIG. 3 shows a typical uni-directional current transformer and secondary circuit. The current transformer primary T.sub.cp has a single turn. The primary turn is thus in series with a line to be monitored.
The current transformer secondary T.sub.sc has a larger number of turns, which are terminated in resistor R via diode D1. The intention is that a true voltage analogue of the primary forward current pulse I.sub.p be developed across R. D1 blocks a reverse recovery voltage. However, it will be seen from FIGS. 4a and 4b that the secondary waveform is distorted as a result of the magnetizing current component.
FIG. 4a illustrates the applied all positive primary current pulse I.sub.p. FIG. 4b depicts the corresponding secondary current analogue pulse developed across R. The effect of two values of secondary magnetizing current, a small value I.sub.mag1 and a large value I.sub.mag2, details how the magnetizing current is effectively subtracted from the ideal transformed current analogue I.sub.s(ideal). From this diagram it is clear that if the peak value of the current at the end of the conduction pulse, I.sub.p, is to be useful for current-limiting purposes, then the secondary shunt inductance of the current transformer must be large enough to ensure that at least a positive slope remains on the net secondary waveform. This means that a sizeable secondary inductance is needed, and so a larger number of secondary turns, a larger core, and high-permeability core material are desirable.
A second major factor that influences the current transformer magnetizing current is the magnitude of the secondary voltage. This voltage is the sum of a selected signal voltage V.sub.o and the rectifier diode D1 forward voltage drop. Larger secondary voltages are advantageous (consistent with a good signal-to-noise ratio), however, large values of V.sub.o will result in large magnetizing currents.
If a smaller core is chosen for the current transformer, then to get the required inductance, a larger number of secondary turns will be required. If the number of secondary terms is too large, then there will be significant interwinding capacitance, and the high frequency response (response to narrow current pulses) will be degraded.
FIG. 5 illustrates a basic arrangement of a uni-directional type current monitoring transformer in a single-ended forward converter.
In this example when the primary power transistor Q.sub.1 is on, the forward current in the current transformer primary T.sub.cp takes the start of all windings positive, and the secondary diode D1 conducts. The current in R2 will be a transform of the primary current and an analogue voltage of the primary current will be developed across R2.
When Q1 turns off at the end of the forward current pulse, rapid reset of the current transformer core occurs as D1 acts as a block and the secondary flyback load resistance R1 is high. As a result, the flyback voltage is large, and this gives a rapid core reset between forward pulses. That is, the flux density .beta. returns to a residual value .beta..sub.r during the off time ready for the next forward pulse.
A .beta.H curve as shown in FIG. 6 is used to depict the amount of flux density .beta. which results from increasing the amount of a field intensity H. .beta..sub.r represents the residual flux density of a system such as that presently under consideration when the transformer has been reset. .beta..sub.w, which is the working value of flux density, represents when the transformer has stored energy. .beta..sub.s and -.beta..sub.s represent when the transformer has become saturated.
As shown in FIG. 7 current transformers C.sub.T1, C.sub.T2 may be placed in the drains of FET switches Q1 and Q2. Signals S.sub.1, S.sub.2 produced from each the current transformers C.sub.T1, C.sub.T2 are combined and are used as an input signal S.sub.12 for current controller C.sub.c. Input signal S.sub.12 is used to determine the amount of current which needs to be delivered to the circuit (i.e. Q.sub.1 -Q.sub.4) in the form of a power pulse.
Problems arise in the converter of FIG. 7 when the resonant transition circuit is operating at or towards a no-load situation. As previously mentioned, reverse currents will exist in the FET transistor switches implemented in this circuit, and at light loads the reverse currents become quite substantial.
During normal operation, of the circuit shown in FIG. 7 the switches are on for 50% of the time. This again is different from straight pulse width modulated, PWM, circuitry where the "on", time of the switches can be varied from 50% to 0%. During normal operation when the switch in question is "on" energy is stored in the inductor or the core of the transformer. Therefore, during normal operation when the switch is "on" energy is being stored in the core. When the "on" half cycle is over, and the FET current is gone, the stored energy will come out of the core to produce a reverse voltage on the transformer allowing the transformer to be reset.
At light loads the current at the start of the power pulse will be reverse or negative current, and it may be a heavy reverse or negative current that stays for half the power pulse. In such a situation, this heavy reverse or negative current will reset the current transformer into a heavy negative saturation -.beta..sub.s and a large amount of energy is stored during this negative saturation. When the FET current reaches zero during the power pulse in a positive going transition, the energy that was stored during the reverse or negative current portion (the energy that is stored during the negative saturation of the current transformer) comes out and begins building a floating "pedestal" under the current pulse signal. This causes unstable responses from the current transformers which in turn provides unpredictable and unstable operation of the converter circuit.
To address the preceding problems, the inventor previously filed an application and received, U.S. Pat. No. 5,610,508 which describes a circuit directed to maintaining proper current transformer operation in a resonant transition converter circuit or any circuit having a wide range of reverse current present at a current transformer primary at the beginning of a power pulse.
A circuit described in U.S. Pat. No. 5,610,508 is illustrated in FIG. 8, which is a full bridge resonant transition converter circuit having a fixed frequency, phase shifted mode of operation. The circuit generally operates in a manner similar to the circuit set forth in FIG. 7, and includes switches SW1-SW4 (which in this embodiment are implemented by FET transistor arrangements) with current transformers 10 and 12 associated with switches SW1 and SW2 respectively. The outputs of current transformers 10, 12 are combined and input to a current comparator 14 via input 16 an analog of reference current I.sub.ref is input to current comparator 14 via input 18. Using this information a controller 20 controls the timing at which power pulses are provided to switches SW1-SW4 via inputs 22-28. The circuit switches between diagonal and horizontal conduction. When either pairs of switches SW1 and SW4 or SW2 or SW3 are active diagonal conduction is occurring and power is being transferred from the transformer primary winding 30 to the secondary winding 32 whereby a signal is generated.
It was noted in the U.S. Pat. No. 5,610,508 patent that for such a circuit in situations from light loads to no load, significant current will flow in a reverse direction through switches SW1-SW4. When this occurs instability can enter into the system. Therefore, added to each of current transformers 10 and 12 are current generators 40, 42 and active clamps 44, 46.
The detailed configuration of the current transformer 12, switch SW2, current generator 42 and clamp 46 of FIG. 8, as described in U.S. Pat. No. 5,610,508, is illustrated in FIG. 9a. This discussion regarding the current generator 42 and active clamp 46 was noted to be equally appropriate for the arrangement in connection with switch SW1, current transformer 10, current generator 40 and active clamp 44. It was also noted to be possible that the current generators 40 and 42 and active clamps 44 and 46 may be used alone or in combination to achieve proper current transformer action during light load and no load situations.
The active clamp 46 of U.S. Pat. No. 5,610,508 was disclosed to include extra secondary or auxiliary winding 50 (in addition to the main secondary winding 48 of current transformer 12), diode 52 and FET transistor 54. When switch SW2 receives a drive pulse, FET 54 receives the same drive pulse activating active clamp 46, which acts as a load allowing the current generated due to the reverse or negative primary current I.sub.pri to flow through the current transformer 12. In this manner, instead of developing volt-seconds which upon the primary current becoming positive causes instability, these volt-seconds are not developed, avoiding a large negative voltage, so that normal reset action will take place. While the cited patent noted an active clamp could be implemented on the secondary winding, it required a negative signal, negative source power supply and level shifters.
In addition to active clamp 46, FIG. 9a illustrates current generator 42, provided to generate a predetermined current bias I.sub.bias which functions to counteract undesirable effects of the negative primary current in the current transformer at the start of a power pulse. In this arrangement bias current I.sub.bias, which is a fraction of the primary current I.sub.pri, is added to the secondary of the current transformer 12. For instance, if the transformer ratio is 1 to 40, then a current 1/40 of the primary current is developed as the bias current I.sub.bias to counteract the negative or reverse primary current. In the present example, with a turns ratio of 1 to 40, providing a current 1/40th of the primary current I.sub.pri results in a ampere-turns NI of magnetizing force equal to the primary current, NI=40.times.1/40, i.e. 1.
Current generator 42 switches bias current I.sub.bias into the current transformer secondary during the power pulse to offset the negative or reverse primary current which occurs at the beginning of a power pulse which may occur due to a shunt inductance found in power transformers and/or a resonant inductor used in such systems. At "absolute no-load" the negative portion of I.sub.pri can last for .PI./2 radians. By injecting the appropriate bias current the positive current pulse can start at 0 radians. FIG. 9b shows the primary current I.sub.pri of current transformer 12. From t.sub.0 to t.sub.1 the primary current is flowing in a negative or reverse direction causing the current transformer core to be saturated into the negative region. Starting at t.sub.1 the current changes to positive going. However, due to the negative or reverse primary current, the output of the current transformer 12 will have a false "pedestal" which causes unstable operation. This is what will be expected without the use of the bias current (and/or the active clamp).
By supplying bias current I.sub.bias, as seen in FIG. 9c, the primary current I.sub.pri is shifted up such that at t.sub.0 the current is at zero (0), i.e. no longer negative at the beginning of the power pulse.
The present invention provides a new and improved active clamp circuit which is implemented with a smaller number of parts, is more economical and which is more efficient than the existing active clamp used to maintain proper current transformer operation.